Every tool shows its working, runs in your browser and is free. Pick one to start.

Try it: the time right now, in binary. Add up the lit bits in each row to read the hours, minutes and seconds.

--:--:--

ConverterHex, binary, decimal and 2's complement up to 128 bits, with Verilog literals. ALUAdd, subtract, multiply, shift and rotate with N, Z, C and V flags. MOSFETOperating point, gm, ro, gm/Id, fT and curves for NMOS and PMOS. RISC-VC to RV32IMC, a register-by-register trace, RTL export and a disassembler. Pipeline5-stage pipeline diagram with forwarding, stalls, flushes and CPI. TimingSetup and hold slack, Fmax, clock skew and how to fix violations. FSM designerState diagram, encoding, minimized equations and Verilog. CMOS gate builderBoolean expression to a transistor schematic, sizing and logical effort. Linux for chip designInstall guides for 10 open-source EDA tools, plus commands and a practice shell. PracticeGATE, interview and viva questions with worked answers you can check in the tools.

Operand A

Operand B

Arithmetic

Logic

Shift and rotate (B is the shift count)

Example values are loaded: 0x7F + 0x01 shows signed overflow. Edit anything.

Program

Compressed (C extension) Max steps

RV32IMC instructions

Register status

Hide zero registers

Export for your RTL testbench

Load the program into your own RV32 core and check it against this simulator. Code starts at address 0. Globals live at 0x2000 and are written by the startup code, so the image below is all your instruction memory needs. The stack pointer starts at 0x10000.

Entry width

Disassembler

Paste machine code from a waveform, a memory dump or a .hex file. 8 hex digits is a 32-bit instruction, 4 digits a 16-bit compressed one. 0x, @address lines and // comments are fine.

00a00513  // li a0, 10
4581      // c.li a1, 0
00b50633
02c585b3
8082

Memory image: read it as a byte stream (a 32-bit instruction can start mid-word)

Instruction trace

Data memory at this step

How this works

C source goes through a small built-in compiler that targets RV32IM, then an assembler encodes every instruction. With the C extension on, instructions that have a 16-bit form (c.addi, c.li, c.mv, c.lwsp, c.beqz and so on) are stored in 2 bytes and the code shrinks. Branch offsets are recomputed for the shorter layout.

The simulator runs the program and records the register file after every instruction. Drag the slider to see the registers at any step. Changed registers are highlighted. x0 always reads 0. The stack starts at 0x10000 and the program ends when main returns or runs ecall with a7 = 93.

The C compiler supports int, unsigned, arrays, pointers, globals, functions, if, while, do, for, break and continue. It does not do floating point, structs, strings, or optimization beyond simple immediates. Output is easy to read but not what an optimizing compiler such as GCC would produce.

Program

Branch predictor

Pipeline diagram

Branch prediction

Hazards in this window

Describe the machine

How to write it

inputs: x, y and outputs: z name the signals.

S0 -> S1 : x & !y moves from S0 to S1 when the condition is true. Leave out the condition for "always".

Moore output: S2 [z] sets z = 1 in S2.
Mealy output: S3 -> S1 : x / z sets z = 1 on that transition.

Operators: ! not, & and, | or, ^ xor. The first state is the reset state, or set reset: S0. # starts a comment.

State diagram

Circles are states, with the Moore outputs inside and the state code under each one. Arrows show the condition, and for a Mealy machine the outputs after the slash.

State table

State encoding

Next-state and output equations

Verilog

Module

Try an input sequence

Boolean function

Output =

Minimize first (fewest transistors) Don't cares

Operators: . or & and, + or | or, ' or ! not, ^ xor, parentheses. So a.b + c' and a&b | !c both work. Start with !( … ) to build one inverting gate. Minterms work too: m(1, 3, 5) + d(7) or F(a, b, c) = m(…).

Transistor schematic

The NMOS pull-down network conducts when the function inside the gate is 1, so a static CMOS gate always inverts. AND terms become NMOS in series and OR terms become parallel branches; the PMOS pull-up network is the dual, with series and parallel swapped. When the output you want is not inverted, an inverter follows the complex gate.

Truth table

Sizing and logical effort

01 / About usSilicon University, Bhubaneswar

Free chip-design tools that show their working.

VLSI_Toolkit is a free set of tools for students and engineers who work on digital and analog chip design. It is built at Silicon University, Bhubaneswar, by two students and their faculty mentor.

Chip design work is full of small calculations that are easy to get wrong: a sign bit at the wrong width, a slack with the skew added the wrong way, a forwarding path that does not exist. Each tool here does one of those jobs, shows its working, and explains the result in plain words, so you learn the method instead of only copying the answer.

Meet the team How we test

Floorplan · what is on the sitedie 1 of 1

03 · analogMOSFETOperating point, small-signal parameters and curves for NMOS and PMOS across four process nodes. 04 · cpuRISC-VC to RV32IMC compiler, assembler and simulator with a register trace. 05Pipeline5-stage diagram: hazards, forwarding, stalls, CPI. 06TimingSetup and hold slack, Fmax, skew. 01ConverterBinary, hex, decimal, 2's complement to 128 bits. 02ALUEvery operation with N, Z, C, V flags. 07FSMState machine to equations and Verilog. 08CMOS gateBoolean expression to transistor schematic. 09 · io ringLinux for chip designTested install guides for 10 open-source tools, from Icarus Verilog to OpenLane 2, plus commands and a practice shell.

Each block is one tool, sized roughly by how much it does. Click a block to open it.

02 / How we workthree rules

Shows its working

Every answer comes with the steps and a plain-words explanation, so you learn the method, not just the number.

Checked before every release

Every tool runs a test suite before a release. The RISC-V output is checked against a Verilog model running in Icarus Verilog, the instruction decoder is round-trip tested on 200,000 random instructions, and every night fresh random cases are checked against independent references. The install guides on the Linux page are run, command by command, on fresh Ubuntu 24.04 and 22.04 machines every night too.

Private by design

Everything runs in your browser. Nothing you type, compile or calculate is sent to a server.

The MOSFET model uses textbook equations that are listed on the page. If you find a wrong answer, please tell us on the contact page.

03 / The teamtwo students and a mentor

Pratyush Kumar Sahu

Idea and implementation

B.Tech, Electronics and Communication Engineering, Silicon University, Bhubaneswar (2023–2027)

Pratyush came up with the idea for VLSI_Toolkit and built it. He works on RTL design and verification in Verilog and SystemVerilog. His projects include a 5-stage pipelined RV32I processor with hazard detection and forwarding, a hybrid Radix-4/8 Booth multiplier for low-power edge AI, and RV32I core integration for the national 1-TOPS RISC-V SoC tape-out programme, where his team was selected among the top 37 of more than 550.

GitHub · LinkedIn

Achyutananda Khanda

Implementation and testing support

M.Sc. VLSI Design, Silicon University, Bhubaneswar (2025–2027)

Achyutananda helped implement and test the tools, bringing hands-on experience in RTL design and functional verification with Verilog. His work includes an RTL digital-twin framework for aging-aware ALUs and multipliers, published at IEEE EDKON 2026, an 8-bit mini CPU, an FSM-based traffic-light controller and a UART transmitter and receiver with parity checking.

GitHub · LinkedIn

Joy Chowdhury

Mentor, technical material and information

Assistant Professor, Department of Electronics and Communication Engineering, Silicon Institute of Technology, Bhubaneswar

Joy Chowdhury mentored the project and provided the technical material and information behind the tools. His research covers advanced CMOS device–circuit co-design, tunnel-FET devices and biosensors, low-power architectures, ASIC design and hardware security. He holds an M.Tech in VLSI Design and Embedded Systems from KIIT University and has submitted his Ph.D. at NIT Rourkela.

Publications on IEEE Xplore

04 / Advisors and well-wishersguidance behind the project

Our esteemed advisors and well-wishers: senior academics in VLSI and electronics whose guidance and good wishes stand behind this project.

Prof. Kamalakanta Mahapatra

Advisor

Professor (HAG), Department of Electronics and Communication Engineering, NIT Rourkela

A pioneer of chip and system design education in Odisha. He has been a professor at NIT Rourkela since 2004, served as Dean of Academics (2017–2019) and Dean of Alumni Affairs, and headed the ECE department several times. He chairs the IEEE Consumer Technology Society, Odisha Chapter, served on the DATE 2022 Technical Programme Committee and received the J. C. Bose award in 2014 for the best engineering-oriented research of the institute.

Publications on IEEE Xplore

Prof. (Dr.) Angsuman Sarkar

Advisor

Professor and Head, Department of Electronics and Communication Engineering, Kalyani Government Engineering College, West Bengal

More than 23 years of teaching and research in short-channel effects of sub-100 nm MOSFETs and nano-device modelling. M.Tech in VLSI and Microelectronics and Ph.D. from Jadavpur University. Senior Member of IEEE, Fellow of IE (India) and IETE, and former Chairman of the IEEE Electron Devices Society, Kolkata Chapter. Author of 15 books and over 130 journal papers, listed among the world's top 2% scientists (Stanford–Elsevier) and honoured with the Shiksha-Ratna Award 2025 by the Government of West Bengal.

Publications on IEEE Xplore

Dr. Jitendra Kumar Das

Advisor

Associate Professor, School of Electronics Engineering, KIIT University, Bhubaneswar

His work spans VLSI design, device modelling, signal processing, embedded systems and communication engineering, from CNTFET-based SRAM cell design to tunnel-FET biosensor modelling and IoT systems for 6G.

Publications on IEEE Xplore

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Privacy policy

Last updated 6 October 2026

The calculators run entirely in your browser. The values, code and programs you enter are not uploaded or stored on any server.

Stored on your device

The site remembers only two preferences in your browser's local storage: light or dark mode, and the phone or desktop layout. Everything else starts fresh on every visit. To keep a setup, use the Share button, which puts your inputs in a link.

Fonts

Fonts load from Google Fonts, which receives your IP address as part of a normal web request.

Contact

Messages from the contact form are sent through our Google Apps Script to our Gmail account and kept in our Google Sheet. We use your email address only to reply.

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VLSI_Toolkit is free, with no sign-up, built by students and their mentor. If a tool saved you time before an exam, a lab or a tape-out, a chai helps us keep building.

₹Your choice

Payments go by UPI straight to Pratyush Kumar Sahu. Your email is used only to send one thank-you note and is never shared. Thank you for supporting free learning tools.

Aa raha hai, thoda wait karo ☕

Practice

GATE ECE, VLSI interviews, lab vivas: every question that haunts you at 2 AM the night before the exam, sorted. Each answer is worked out step by step, and you can check it in our tools. No more "sir, answer key mein galat hai". No more "bhai, notes bhej de" either.

Two are planning, one is welding. Classic group project, except this time all three are actually working.

What's on the way

2's complement drills, so when the examiner asks "sign bit kidhar hai?", your brain does not overflow.
CMOS sizing and MOSFET regions, so simple that even the last bench goes from cut-off to saturation.
Setup/hold, pipeline hazards and FSM problems: exam favourites, step by step. Negative slack is allowed only in your sleep schedule.
RISC-V assembly puzzles you can run in the simulator. "It worked in my head" is no longer an excuse.

Want a topic first? Tell us, chai pe charcha karenge ☕. Till then, warm up on the timing calculator or the FSM designer.

About us

Value

Bits. Tap to flip. Sign bit outlined.

Quick actions

Floating point (IEEE 754)

Fixed point (Q format)

Negate steps (2's complement)

RTL literals

Encodings of this bit pattern

Resize

Arithmetic

Logic

Shift and rotate (B is the shift count)

Device

Bias magnitudes, so PMOS uses positive numbers too

Size from a target

Curves

CMOS inverter

Analog VLSI notes

Program

RV32IMC instructions

Register status

Export for your RTL testbench

Disassembler

Program

Pipeline diagram

Branch prediction

Hazards in this window

Timing path

Clock

Launch flip-flop

Combinational logic

Capture flip-flop

Clock network

Result

Timing diagram

Calculation

Describe the machine

State diagram

State table

State encoding

Next-state and output equations

Verilog

Try an input sequence

Boolean function

Transistor schematic

How it was minimized

Truth table

Sizing and logical effort

01 / About usSilicon University, Bhubaneswar

02 / How we workthree rules

Shows its working

Checked before every release

Private by design

03 / The teamtwo students and a mentor

Pratyush Kumar Sahu

Achyutananda Khanda

Joy Chowdhury

04 / Advisors and well-wishersguidance behind the project

Prof. Kamalakanta Mahapatra

Prof. (Dr.) Angsuman Sarkar

Dr. Jitendra Kumar Das

Contact us

Privacy policy

Stored on your device

Fonts

Contact

Buy us a chai

Buy us a chai

Paid? Get your thank-you note 💌

Practice

What's on the way

Paid? Get your thank-you note